- 计算机组成与设计(硬件软件接口英文版原书第5版ARM版)/经典原版书库
- - 作者：(美)戴维·A.帕特森//约翰·L.亨尼斯|责编:曲熠
  - 出版社：机械工业
  - ISBN：9787111668350
  - 出版日期：2021/01/01
  - 页数：697
- 售价：67.6

内容大纲
本书采用ARMv8-A体系结构, 介绍当前硬件技术的基本原理、汇编语言、计算机算术、流水线、内存层次结构和I/O。本书更加关注后PC时代发生的变革，通过实例、练习等详细介绍最新涌现的移动计算和云计算，更新的内容还包括平板电脑、云基础设施以及ARM（移动计算设备）和x86（云计算）体系结构。
作者介绍
目录
CHPTERS
1 Computer bstractions and Technology
  1.1  Introduction
  1.2  Eight Great Ideas in Computer rchitecture
  1.3  elow Your Program
  1.4  Under the Covers
  1.5  Technologies for uilding Processors and Memory
  1.6  Performance
  1.7  The Power Wall
  1.8  The Sea Change: The Switch from Uniprocessors to Multiprocessors
  1.9  Real Stuff: enchmarking the Intel Core i
  1.10  Fallacies and Pitfalls
  1.11  Concluding Remarks
  1.12  Historical Perspective and Further Reading
  1.13  Exercises
2 Instructions: Language of the Computer
  2.1  Introduction
  2.2  Operations of the Computer Hardware
  2.3  Operands of the Computer Hardware
  2.4  Signed and Unsigned Numbers
  2.5  Representing Instructions in the Computer
  2.6  Logical Operations
  2.7  Instructions for Making Decisions
  2.8  Supporting Procedures in Computer Hardware
  2.9  Communicating with People
  2.10  LEGv8 ddressing for Wide Immediates and ddresses
  2.11  Parallelism and Instructions: Synchronization
  2.12  Translating and Starting a Program
  2.13  C Sort Example to Put it ll Together
  2.14  rrays versus Pointers
  2.15  dvanced Material: Compiling C and Interpreting Java
  2.16  Real Stuff: MIPS Instructions
  2.17  Real Stuff: RMv7 (32bit) Instructions
  2.18  Real Stuff: x86 Instructions
  2.19  Real Stuff: The Rest of the RMv8 Instruction Set
  2.20  Fallacies and Pitfalls
  2.21  Concluding Remarks
  2.22  Historical Perspective and Further Reading
  2.23  Exercises
3 Arithmetic for Computers
  3.1  Introduction
  3.2  ddition and Subtraction
  3.3  Multiplication
  3.4  Division
  3.5  Floating Point
  3.6  Parallelism and Computer rithmetic: Subword Parallelism
  3.7  Real Stuff: Streaming SIMD Extensions and dvanced Vector Extensions in x
  3.8  Real Stuff: The Rest of the RMv8 rithmetic Instructions
  3.9  Going Faster: Subword Parallelism and Matrix Multiply
  3.10  Fallacies and Pitfalls

  3.11  Concluding Remarks
  3.12  Historical Perspective and Further Reading
  3.13  Exercises
4 The Processor
  4.1  Introduction
  4.2  Logic Design Conventions
  4.3  uilding a Datapath
  4.4  Simple Implementation Scheme
  4.5  n Overview of Pipelining
  4.6  Pipelined Datapath and Control
  4.7  Data Hazards: Forwarding versus Stalling
  4.8  Control Hazards
  4.9  Exceptions
  4.10  Parallelism via Instructions
  4.11  Real Stuff: The RM Cortex53 and Intel Core i7 Pipelines
  4.12  Going Faster: InstructionLevel Parallelism and Matrix Multiply
  4.13  dvanced Topic: n Introduction to Digital Design Using a Hardware Design Language to Describe and Model a Pipeline and
More Pipelining Illustrations
  4.14  Fallacies and Pitfalls
  4.15  Concluding Remarks
  4.16  Historical Perspective and Further Reading
  4.17  Exercises
5 Large and Fast: Exploiting Memory Hierarchy
  5.1  Introduction
  5.2  Memory Technologies
  5.3  The asics of Caches
  5.4  Measuring and Improving Cache Performance
  5.5  Dependable Memory Hierarchy
  5.6  Virtual Machines
  5.7  Virtual Memory
  5.8  Common Framework for Memory Hierarchy
  5.9  Using a FiniteState Machine to Control a Simple Cache
  5.10  Parallelism and Memory Hierarchy: Cache Coherence
  5.11  Parallelism and Memory Hierarchy: Redundant rrays of Inexpensive Disks
  5.12  dvanced Material: Implementing Cache Controllers
  5.13  Real Stuff: The RM Cortex53 and Intel Core i7 Memory Hierarchies
  5.14  Real Stuff: The Rest of the RMv8 System and Special Instructions
  5.15  Going Faster: Cache locking and Matrix Multiply
  5.16  Fallacies and Pitfalls
  5.17  Concluding Remarks
  5.18  Historical Perspective and Further Reading
  5.19  Exercises
6 Parallel Processors from Client to Cloud
  6.1  Introduction
  6.2  The Difficulty of Creating Parallel Processing Programs
  6.3  SISD,MIMD,SIMD,SPMD,and Vector
    Hardware Multithreading
    Multicore and Other Shared Memory Multiprocessors
    Introduction to Graphics Processing Units
    Clusters, Warehouse Scale Computers, and Other MessagePassing

  6.8  Introduction to Multiprocessor Network Topologies
  6.10  Multiprocessor enchmarks and Performance Models
  6.11  Rea Stuf. enchmarking and Roofines ofthe ntel Corei7960 and the NVIDI Tesla GPU
  6.12  Going Faster:M ultiple Processors and Matrix M ultiply
  6.13  Fallacies and Pitfalls
  6.14  Concluding Remarks
  6.15  Historical Perspective and Further Reading
  6.16  Exercises
APPENDIX
A  The Basics of Logic Design
  A.1  Introduction
  A.2  Gates,Truth Tables,and Logic Equations
  A.3  Combinational Logic
  A.4  Using a Hardware Description Language
  A.5  Constructing a asic rithmetic Logic Unit
  A.6  Faster ddition:Carry Lookahead
  A.7  Clocks
  A.8  Memory Elements:FlipFlops,Latches,and Registers
  A.10  FiniteState Machines
  A.11  Timing Methodologies
  A.12  Field Programmable Devices
  A.13  Concluding Remarks
  A.14  Exercises
Index I
ONLINE CONTENT
B  Graphics and Computing GPUs
  B.1  Introduction
  B.2  GPU System rchitectures
  B.3  Programming GPUs
  B.4  Multithreaded Multiprocessor rchitecture
  B.5  Parallel Memory System
  B.6  Floating Point rithmetic
  B.7  Real Stuff:The NVIDI GeForce
  B.8  Real Stuff:M apping pplications to GPUs
  B.9  Fallacies and Pitfalls
  B.10  Concluding Remarks
  B.11  Historical Perspective and Further Reading
C  Mapping Control to Hardware
  C.2  Implementing Combinational Control Units
  C.3  Implementing Finite-State Machine Control
  C.4  Implementing the Next-State Function with a Sequencer
  C.5  Translating a Microprogram to Hardware
  C.6  Concluding Remarks
  C.7  Exercises
D  A Survey of RISC Architectures for Desktop,Server and Embedded Computers
  D.1  Introduction
  D.2  Addressing Modes and Instruction Formats
  D.3  Instructions:The MIPS Core Subset
  D.4  Instructions:M ultimedia Extensions of the Desktop/Server RISCs
  D.5  Instructions: Digital Signal-Processing Extensions of the Embedded RISCS

  D.6  Instructions: Com mon Extensions to MIPS Core
  D.7  Instructions Unique to MIPS-64
  D.8  Instructions Unique to Alpha
  D.9  Instructions Unique to SPARCv9
  D.10  Instructions Unique to PowerPC
  D.11 Instructions Unique to PA-RISC 2.0
  D.12  Instructions Unique to ARM
  D.13  Instructions Unique to Thumb
  D.14  Instructions Unique to SuperH
  D.15  Instructions Unique to M32R
  D.16  Instructions Unique to MIPS-16
  D.17  Concluding Remarks
Glossary
Further Reading

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